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FPGA Architecture and Programming using Verilog HDL

Registrations open for  Batch 13

                      Course Overview

We will be sending a welcome email to the registered email one day prior to the Workshop Start Date . Please check the inbox as well as spam folder of your registered email ID on this date. This email will carry all details needed for you to access this Workshop .This course will not appear in the NPTEL Basket. For detailed list of answers on FAQs please refer Workshop FAQ.

Important Dates

 
Event Date
Registration closing date 02-Jul-2026
First Come First Served Basis
Wiil be closed once batch is full
Sharing of Course link Registered candidates will get credentials to access the course in their registered email ID on the previous day of the course start date .
Course Start date 06-07-2026
Duration 75 Hours (Theory: 15 hours & Lab : 60 hours) 24X7 Self-paced using Recorded Lectures

 

Support Team

  1. Workshop Coordinator:  Mr Sreejeesh, STO . Email :sree@calicut.nielit.in, sreejeesh@nielit.gov.in. Ph# 94477 69756
  2. For Queries/Support : Ms Nanditha Varma, Adhoc Faculty, Email :nanditha[at]calicut[dot]nielit[dot]in. 

 

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