Course Description

This four-week internship program provides hands-on training in FPGA based digital system design using Verilog HDL. The program introduces students to modern hardware design methodologies used in VLSI and FPGA development.

Participants will learn RTL design using Verilog HDL, simulation and verification techniques, and the complete FPGA design flow including synthesis, implementation and bitstream generation. Students will gain practical experience implementing digital circuits on FPGA boards through guided laboratory sessions and mini-projects.

Key Topics Covered

• Digital Design Fundamentals
• Introduction to FPGA Architecture
• Verilog HDL – RTL Coding
• Combinational Logic Design
• Finite State Machine (FSM) Design
• Simulation and Verification using FPGA Tools
• Synthesis, Implementation and Bitstream Generation
•  FPGA Programming and Hardware Testing

Duration
B. Tech – 4 Weeks
M. Tech -6 Weeks
Eligibility
B. E / B.Tech students (Electronics / Electrical / Computer Science / Instrumentation or related
branches) – Ongoing Final year or Pre-final year.
*B. Tech Course completed students are not eligible for the Internship.
Seats Available
60 seats in batch 1 and 40 Seats in batch 2 (Selection based on First-Come First-Served basis)

Important Dates

Batch	Starting Date	Ending Date	Batch Size	Apply
Batch 1	11 May 2026	05 June 2026	60	Closed
Batch 2	08 June 2026	03 July 2026	40	Apply Now - MTech  Apply Now - BTech

 

 

 

NOTE: Candidates should bring Laptops compulsorily.

Internship Modules

• Week 1 – Digital Design Basics and Verilog Programming
• Week 2 – Combinational and Sequential RTL Design
• Week 3 – FPGA Architecture and Implementation Flow
• Week 4 – FPGA Prototyping Project and Demonstration-Mini Project
• Week 5 & 6 – Mini Project only for M.Tech Candidates (Online mode -with Remote Lab support)

Fee Structure

• Course Fee (Without Hostel): ₹ 5,000 (B.Tech) / ₹ 8,000 (M.Tech)
• Course Fee (With Hostel): ₹ 6,600 (B.Tech) / ₹ 9,600 (M.Tech)

Certification
A digitally signed internship certificate will be issued to participants who successfully complete the internship program.

Coordinator

Sreejeesh S G,
Senior Technical Officer
Email: sreejeesh[at]nielit[dot]gov[dot]in  
Phone: +91 9447769756

Terms and Conditions

• The course schedule does not include Saturdays, Sundays, and declared holidays.
• The entire course fee must be paid before the commencement of the program.
• No refund will be provided if a registered candidate fails to attend the offline sessions.
• If the program is postponed or cancelled due to unforeseen circumstances from the institute’s side, the course fee will be refunded if the revised schedule is not convenient for the participant.

All participants must adhere to the rules and regulations of the institute during the internship.