Verilog HDL Language and Coding for Synthesis

Date: 1st March– 12th March 2021

Course Description: The objective of the course is to provide a thorough understanding about and hands-on with digital design & Verification using Verilog HDL . The Course is planned with instructor led Offline/live sessions of lectures and demonstrations.

Who can attend?

Anyone who is interested in digital front end VLSI Design

  • Preferably Students pursuing  Engineering , 

Course Duration : 10  days

Course Fee: Rs 3900/-
Course Start Date:  1st March 2021
Last Date for Registration and Payment: 28th February 2021

Course Contents :

  • Modeling Concepts
  • Lexical Conventions & Data Types
  • System Tasks & Compiler Directives
  • Modules, Ports and Module Instantiation Methods
  • Gate Level Modeling
  • Dataflow Modeling
  • Behavioral Modeling
  • RTL Design and Logic Synthesis and Synthesis issues
  • Design Verification using Test benches
  • Mini-project /Case Studies

Faculty Profile

Qualification and experience of the faculty handling the sessions

  1. Nandakumar.R – Scientist/Engineer ‘D’
  2. Sreejeesh S.G – Senior Technical Officer

Course Coordinator

Nandakumar.R , Scientist/Engineer ‘D’ , 9995427802 (Whatsapp) ,

Certificate: Certificate to all completed candidates

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Terms and Conditions 

  1. In case any registered candidate could not attend the online session due to technical issue at their side there will not be any refund of the course fee and the sessions will not be repeated.
  2. In case the online course is cancelled /postponed due to some technical issue at NIELIT side and new date is not convenient to the candidate, our liability is limited to the refund of the course fee and NIELIT shall not be responsible for any    consequential damages.

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For any queries email to mailto: itcourses[at]calicut[dot]nielit[dot]in

 or contact 04952287266/9446732691 (during 9.00 AM to 5.30 PM)

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